1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly to a pin contact test for a semiconductor integrated circuit in which a plurality of chips are packaged in the same package.
2. Description of the Background Art
With the advent of the multimedia age, equipment systems are enlarged in scale but at the same time strongly required to be reduced in size and weight. Since a high integration only through a miniaturized process of LSI (Large Scale Integrated Circuit) is limited, a high density packaging technique such as a multi chip package is generally used in recent years.
FIG. 12 is a schematic illustration of a multi chip package. Two chips CA and CB will be described with reference to FIG. 12 as well as in the following.
In this multi chip package, the upper chip CA and the lower chip CB are respectively arranged above and below. Each of chips CA and CB has a plurality of pads PAD, and in each of chips CA and CB, pads PAD are connected to their respective external pins PIN by wire bonding. This structure as a whole is then sealed with a molding compound such as epoxy resin. In this way, in a multi chip package, an external pin PIN is generally shared among multiple chips.
In the semiconductor integrated circuit in multi chip package as described above, however, it is extremely difficult to conduct a pin contact test.
In FIG. 12, for example, an attention will be paid to an external pin PIN0 and it is assumed that a wire W0 connecting a pad PAD0 on chip CA to external pin PIN0 is disconnected while a wire W0# connecting a pad on chip CB to external pin PIN0 is normal. When a conduction test for detecting a contact failure is performed using external pin PIN0, it is difficult to detect this failure in spite of the failure on the side of chip CA because chip CB is normally operated. Furthermore, even if a failure is detected, it is difficult to specify which chip is defective.